$include (defines.inc)

	org		0000h
	ajmp 	start

	org		serial_rt
	clr		ie.4
	ajmp	uart_irq

	org		Int6_rt
	clr		IE01.0
	ajmp	spi_irq

	org		Int7_rt
	clr		IE01.1
	AJMP	spi2_irq

	org		Int8_rt
	clr		IE01.2
	ajmp	can_irq

	ORG		Int9_rt
	clr		IE01.3
	AJMP	can2_irq

	ORG		Int10_rt
	clr		IE01.4
	AJMP 	i2c_irq

	org		Int11_rt
	clr		IE01.5
	AJMP	pwm_irq

	org		Program_Start_Address

uart_irq:
	mov		R0,86h			;read iir
	mov		R0,#255d
	
	uart_irq_read:
	mov		P0,84h
	DJNZ	R0,uart_irq_read

	setb		IE.4
	reti

spi_irq:
	MOV		SPI_SR,#00000000B	;CLR irq request

	MOV		R0,7EH
	CJNE	R0,#0D,spi_1
	MOV		SPI_CR,#11000011B	;set 4 bytes trigger one irq
	MOV		SPI_DATA,#0A1h
	MOV		SPI_DATA,#0A2h
	MOV		SPI_DATA,#0A3h
	MOV		SPI_DATA,#0A4h
	INC		R0
	MOV		7EH,R0
	AJMP	spi_irq_end

	spi_1:
	CJNE	R0,#1D,spi_2
	setb	P3.4				;DISABLE SLAVE'S NSS SIGNAL
	MOV		P0,SPI_DATA
	MOV		P0,SPI_DATA
	MOV		P0,SPI_DATA
	MOV		P0,SPI_DATA			;READ DUMMY BYTES
	MOV		SPI_CR,#11000000B	;SET 1 BYTES TRIGGER ONE IRQ
	CLR		P3.4				;ENABLE SLAVE
	MOV		SPI_DATA,#80H		;WRITE READ ADDRESS
	INC 	R0
	MOV		7EH,R0	
	AJMP	spi_irq_end

	spi_2:
	CJNE	R0,#2D,spi_3
	MOV		P0,SPI_DATA			;READ DUMMY BYTES
	MOV		SPI_CR,#11000011B	;4 BYTES TRIGGER 1 IRQ
	MOV		SPI_DATA,#12H
	MOV		SPI_DATA,#23H
	MOV		SPI_DATA,#34H
	MOV		SPI_DATA,#45H	;FOR READ,WRITE 4 DUMMY DATA
	INC		R0
	MOV		7EH,R0
	AJMP	spi_irq_end

	spi_3:
	CJNE	R0,#3D,spi_irq_end
	MOV		P0,SPI_DATA
	MOV		P0,SPI_DATA
	MOV		P0,SPI_DATA
	MOV		P0,SPI_DATA
	INC		R0
	MOV		7EH,R0


	spi_irq_end:		   
	SETB	IE01.0
	
	reti

spi2_irq:
	MOV		SPI2_SR,#00000000B
	MOV		P0,SPI2_DATA
	SETB	IE01.1

	RETI

can_irq:
  	MOV		EO,#00000000B
	MOV		A,0DCH		;clr irq request
	JZ		can_irq_end		;no interrupt, exit irq
	
	MOV		R0,A		
	ANL		A,#00000010b	;test if transmit interrupt
	JNZ		can_trans_irq
	MOV		A,R0
	ANL		A,#00000001b	;test if receive interrupt
	JNZ		can_receive_irq
	AJMP	can_irq_end

	can_trans_irq:
	MOV 	P0,#0A8H
	AJMP	can_irq_end
	
	can_receive_irq:
	MOV		P0,0E6H
	MOV		P0,0E7H
	MOV		P0,0E9H
	MOV		P0,0EAH

	MOV		0DAH,#00000100B	//release buffer to clr the receive irq.

	can_irq_end:
	SETB	IE01.2
	reti

can2_irq:
	MOV		EO,#10000000B 
  	MOV		A,0DCH		;clr irq request
	JZ		can2_irq_end		;no interrupt, exit irq
	
	MOV		R0,A		
	ANL		A,#00000010b	;test if transmit interrupt
	JNZ		can2_trans_irq
	MOV		A,R0
	ANL		A,#00000001b	;test if receive interrupt
	JNZ		can2_receive_irq
	AJMP	can2_irq_end

	can2_trans_irq:
	MOV 	P0,#0A8H
	AJMP	can2_irq_end
	
	can2_receive_irq:
	MOV		P0,0E6H
	MOV		P0,0E7H
	MOV		P0,0E9H
	MOV		P0,0EAH

	MOV		0DAH,#00000100B	//release buffer to clr the receive irq.

	can2_irq_end:
	SETB	IE01.3
	reti

i2c_irq:
	mov		9eh,#01h	;clear interrupt flag in i2c control register
	
	mov		R0,7fh
	CJNE	R0,#3fH,i2c_read

	mov		P0,9Dh		;read RXR last bit
	ajmp	i2c_irq_end

	i2c_read:
	CJNE	R0,#3eh,i2c_write
	mov		P0,9Dh		;read RXR
	mov		9eh,#01101000b		;set command ( read, nack_read, stop)
	inc		R0
	mov		7fh,R0
	ajmp	i2c_irq_end

	i2c_write:
	mov		9dh,@R0
	inc		R0
	mov		9eh,@R0
	inc		R0
	mov 	7fh,R0

	

	i2c_irq_end:			
	SETB	IE01.4
	RETI

pwm_irq:
	MOV		P0,0BFh
	
	SETB	IE01.5
	RETI

start:
	setb	IE.7	;enable all interrput

;begin uart test
	setb	IE.4			;enable interrupts
	mov		98h,#10000000b	;set LCR.7=1, for access PRER
	mov		85h,#00h		;prer_high byte
	mov		84h,#01h		;prer_low byte
	mov		98h,#00011011b 	;write LCR, prity even, 1 stop bits, 8bits per byte
	mov		86h,#00h		;FCR, choose rx fifo trigger level
	mov		0A1H,#250d		;rx fifo trigger level
	mov		86h,#10000000b	;set tx fifo trigger level	
	mov		0A1H,#6h		;tx fifo trigger level
	mov		85h,#00000101b	;enable interrupts

	mov 	R1,#255d

	uart_loop:
	mov		84h,R1
	djnz	R1,uart_loop		

;begin	i2c test
	;prepared for send data
	mov		30h,#01h		;slave mem address
	mov		31h,#10h	    ;write slave

	mov		32h,#0a5h		;slave mem data
	mov		33h,#10h		;write slave

	mov		34h,#5ah		;slave mem data
	mov		35h,#50h		;write slave & stop (last byte)

	;read from i2c slave
	mov		36h,#00100000b	;salve address
	mov		37h,#90h		;set command (start & write)

	mov		38h,#01h		;salve mem address
	mov		39h,#10h		;write slave

	mov		3Ah,#00100001b	;slave address and read-bit
	mov		3Bh,#90h		;set command(start , write) (this is a repeat start)

	mov		3Ch,#00h		;dummy. 
	mov		3dh,#20h		;set command(read, ack_read)
	
	mov		3eh,#00h		;dummy

	setb	IE01.4
 	mov		9ah,#200d		 ;write prescaler low byte
	mov		9bh,#00d		;write prescaler hi byte

	mov		9ch,#0c0h		;write control register enable core,enable irq
	;write slave
	mov 	9dh,#00100000b	;write txr, slave address and write-bit
	mov		9eh,#90h		;write command register: start & write
	mov		7fh,#30h
																

;begin uart test
	mov		SBUF,#10110101b


;begin pwm test
	setb	IE01.5
	MOV		0ADh,#088h
	MOV		0AEh,#088H
	MOV		0AFh,#099h
	MOV		0BAh,#099h
	MOV		0BBh,#0aah
	MOV		0BCh,#0aah
	mov		0bdh,#0bbh
	mov		0beh,#0bbh		   ;write comparator register 0 to 3

	mov		0a3h,#00h			;write prer register
	;write comparator control register
	mov		0a5h,#10001000b		;enable,edge-aligned,no-reload,irq-enable,pol=0
	mov		0a6h,#10101000b		;enalbe,edge-aligned,reload,irq-enalbe,pol=0
	mov		0a7h,#11001000b
	mov		0aah,#11101000b

	mov		0a4h,#11000000b
	
;begin spi test
	setb	IE01.0	;enable xintr 6
	MOV 	SPI_PRER, #00001000B   ;write prer
	MOV		SPI_CR,#11000000B	   ;write spi enable and interrput enable
	CLR		P3.4					;enable nss
	MOV		7EH,#00
	MOV		SPI_DATA,#0C0h	   ;send write mem signal

;BEGIN SPI2 TEST
	SETB	IE01.1
	MOV		SPI2_PRER,#00011111B
	MOV		SPI2_CR,#11000000B
	MOV		SPI2_DATA,#10101100B

;begin can test
	MOV		EO,#00000000B	;choose can1 register
	setb	IE01.2	;ENABLE XINTR 8
	MOV		0DEh,#00000001B	;write timing0
	MOV		0DFh,#00101111B	;write timing1
	MOV		0F6h,#10000000B	;write clock divider register, extended mode
	MOV		0E6h,#0A6H	;write acceptance code 0 to 3 and mask 0 to 3
	MOV		0E7H,#0B0H	
	MOV		0E9H,#12H
	MOV		0EAH,#30H
	MOV		0EBH,#0FFH
	MOV		0ECH,#0FFH
	MOV 	0EDH,#0FFH
	MOV		0EEH,#0FFH

	MOV		0D9H,#00000100b	;set selftest mode and exit the reset mode
	MOV		0DDH,#0FFH	   ;enable all interrupt

	MOV		0E6h,#83H	;write tx buffer
	MOV		0E7H,#0ABH	
	MOV		0E9H,#0BCH
	MOV		0EAH,#0CDH
	MOV		0EBH,#56H
	MOV		0ECH,#0deH
	MOV 	0EDH,#0adH
	MOV		0EEH,#0beH

	LCALL	DELAY	;delay sometime 

	MOV		0DAH,#00010010B	  	;start selftransmit and don't retry

;begin can2 test
	setb	IE01.3	;ENABLE XINTR 9
	MOV		EO,#10000000B			  ;choose can2 register
	MOV		0DEh,#00000001B	;write timing0
	MOV		0DFh,#00101111B	;write timing1
	MOV		0F6h,#10000000B	;write clock divider register, extended mode
	MOV		0E6h,#0A6H	;write acceptance code 0 to 3 and mask 0 to 3
	MOV		0E7H,#0B0H	
	MOV		0E9H,#12H
	MOV		0EAH,#30H
	MOV		0EBH,#0FFH
	MOV		0ECH,#0FFH
	MOV 	0EDH,#0FFH
	MOV		0EEH,#0FFH

	MOV		0D9H,#00000100b	;set selftest mode and exit the reset mode
	MOV		0DDH,#0FFH	   ;enable all interrupt

	MOV		0E6h,#83H	;write tx buffer
	MOV		0E7H,#12H	
	MOV		0E9H,#23H
	MOV		0EAH,#34H
	MOV		0EBH,#56H
	MOV		0ECH,#0deH
	MOV 	0EDH,#0adH
	MOV		0EEH,#0beH

	LCALL	DELAY	;delay sometime 

	MOV		0DAH,#00010010B	  	;start selftransmit and don't retry

WHILE:	
	AJMP	WHILE

DELAY:
	MOV		R7,#10
D1:	MOV 	R6,#50
D2:	DJNZ 	R6,D2
	DJNZ	R7,D1
	RET



END